The present invention relates to a termination structure provided for a trench DMOS device, and more particularly, to a termination structure provided for a trench DMOS device to reduce occurrence of current leakage and to prevent premature phenomena of voltage breakdown resulting from electric field crowding at the border of the active area and a method of manufacturing the same.
A DMOS (Double diffused MOS) transistor is a type of MOSFET (Metal Oxide Semiconductor Field Effect Transistor) that uses diffusion to form a transistor region. DMOS transistors are typically employed as power transistors for high voltage power integrated circuits.
One particular type of DMOS transistor is a so-called trench DMOS transistor. In this kind of trench MOSFET devices, the channels are arranged in a vertical manner, instead of horizontally as in most planar configurations. FIG. 1 shows a cross-sectional view of a conventional trenched gate MOSFET device 10. The trenched gate MOSFET device 10 includes a trench 12 filled with conductive material 14 separated from the silicon regions 16 by a thin layer of insulating material 18. A body region 20 is diffused in an epitaxial layer 22, and a source region 24 is in turn diffused in the body region 20. Due to the use of these two diffusion steps, a transistor of this type is frequently referred to as a double-diffused metal oxide semiconductor field effect transistor with trench gating or, in brief, a “trench DMOS.” As arranged, the conductive and insulating materials 14 and 18 in the trench 12 form the gate 26 and gate oxide layer 28, respectively, of the trench DMOS.
Aside from a design of active area for carrying large current, it is also required for power transistors to create a termination structure in the periphery of the active region (i.e., at the edge of a die) to prevent premature phenomena of voltage breakdown.
Referring to FIG. 2, a termination structure provided for a trench DMOS device is shown. An N-type epitaxial layer 52 is provided on an N+ substrate 50. The N+ substrate 50 is typically a silicon substrate as well as the N-type epitaxial layer 52.
Trenches 56 formed within the N-type epitaxial layer 52 are lined with a gate oxide layer 58 and filled with polysilicon. The polysilicon in the trenches 56 is defined as gate electrodes 60. Within the N-type epitaxial layer 52 are P− body regions 54. P− body regions 54 in an active area (i.e., between adjacent trenches 56) are referred to herein “active area P body regions”, while P body regions in a termination area (i.e., adjacent to and outside of a trench 56 on the periphery) are referred to as “termination P body regions.” A “peripheral trench” refers to a trench 56, or a portion thereof, which is formed in a surface and is flanked on one side, but not the other, by one or more similar structures.
The edge of the trench DMOS device is a field oxide region 62 formed by the conventional method, wherein the thickness thereof is about 4,000 to 10,000 angstroms, preferably about 60,000 angstroms. The field oxide region 62 insulates portions of upper surfaces of the N-type epitaxial layer 52 and the termination P body regions.
The trench DMOS device of FIG. 2 also includes a plurality of N+ doped regions 64 and P+ contact regions 66, which extend to a depth of about 1.5 to 4.0 microns, preferably about 2.5 microns, within the P− body regions 54. The N+ doped regions 64 are abutting to side walls of the trenches 56 and upper surfaces of the P− body regions 54 in the active area. Between two of the adjacent N+ doped regions 64 being sandwiched a P+ contact region 66, thereby the P+ contact region 66 is abutting to upper surface of the P− body region 54 as well. Furthermore, another P+ contact region 66 is formed within the P− body region 54 between the peripheral trench and the field oxide region 62 (i.e., the termination area).
A plurality of passivation regions 68 (e.g., BPSG layer) principally cover the polysilicon so as to prevent the gate electrodes 60 from being shorted to the N+ doped regions 64. A conductive (e.g., metal) material 70 contacts and grounds the P− body region 54.
A method for manufacturing the trench DMOS device and the termination structure provided therefor is now described in detail. Referring to FIG. 3A, an N-type epitaxial layer 52 is initially grown on an N+ doped substrate 50. Next, an initial oxide layer 61 is grown on the epitaxial layer 52 to a thickness of about 150 to 500 angstroms, preferably about 200 angstroms. A first photoresist layer 72 is then coated on the structure and a first mask (not shown) is used to define patterns of the first photoresist layer 72. Subsequently, the initial oxide layer 61 where not covered by the patterned first photoresist layer 72 is removed by an etching procedure. The remaining first photoresist layer 72 is stripped from the initial oxide layer 61. Then, the initial oxide layer 61 is oxidized to form a field oxide structure 62 over the edge of the substrate 50. The epitaxial layer 52 not covered by the field oxide structure 62 is implanted and diffused to form a P− body region 54 therein. The resulting structure is shown in FIG. 3B.
Referring to FIG. 3C, a second photoresist layer 74 is coated on the structure of FIG. 3B. Next, a second mask (not shown) is used to define patterns of the second photoresist layer 74. A plurality of trenches 56 are formed through the P− body region 54 by using the patterned second photoresist layer 74 as an etching mask. Thereafter, the second photoresist layer 74 is removed. As will be appreciated more fully below, a depth of the trenches 56 is substantially greater than that of the P− body region 54. The resulting structure is shown in FIG. 3D.
Referring to FIG. 3E, a gate oxide layer 58 is attached on the structure of FIG. 3D where not covered by the field oxide structure 62. Subsequently, a polysilicon layer 60 is deposited, typically by CVD, to cover the structure of FIG. 3E and to fill the trenches 56. Thereafter, a third photoresist layer (not shown) is coated on the polysilicon layer 60 and patterns thereof are defined by using a third mask (not shown). The polysilicon layer 60 is then etched through apertures in the third photoresist layer to optimize its thickness within the trenches 56. The resulting structure is shown in FIG. 3F.
Next, a portion of the structure between the peripheral trench and the edge of the substrate 50 (or die) is masked (not shown), and other portion of the structure in the active area is covered by a fourth photoresist layer (not shown). Next, a fourth mask (not shown) is used to define patterns of the fourth photoresist layer. The P− body region 54 where not covered by the patterned fourth photoresist layer is doped to form a plurality of N+ doped regions 64 therein (FIG. 3G). Thereafter, the masking layer and the fourth photoresist layer are removed. It is noted that the N+ doped regions 64 are formed, by implantation and diffusion, within the P− body region 54. The N+ doped regions 64 are abutting to upper surfaces of the P− body region 54 and side walls of the trenches 56 in the active area.
Referring to FIG. 3H, a passivation (e.g., BPSG) layer 68 is grown on the structure of FIG. 3G, upon which is coated a fifth photoresist layer (not shown). Thereafter, patterns of the fifth photoresist layer are defined by using a fifth mask (not shown). The passivation layer 68 is etched through apertures in patterned fifth photoresist layer to form contact holes 69 therein. The fifth photoresist layer is then removed and portions of the P− body region 54 exposed in the contact holes 69 are then doped to form P+ contact regions 66. A conductive layer 70 is formed on the structure and fills the contact holes 69. Next, a sixth photoresist layer (not shown) is coated on the conductive layer 70 and patterned by using a sixth mask (not shown). The conductive layer 70 is etched through the aperture in patterned sixth photoresist layer to expose a part of the passivation layer 68 over the field oxide structure 62. The conductive layer 70 is provided to contact and ground the P− body region 54.
Referring back to FIG. 2, the bird beak characteristic shown in the marked area 76 leads to occurrence of premature phenomena of voltage breakdown since the electric field crowds thereat. In addition, the patterned fourth photoresist layer for forming the N+ doped regions 64 easily peels off from the gate oxide layer 58 since the dimensions thereof are very small.